Publications in 1987-1993
A E Parker and J B Scott,
"Intermodulation nulling in GaAs
MESFETs," Electronic Letters, vol. 29, no. 22,
pp. 1961-1962, 28 Oct. 1993.The Institution Electrical Engineers, (Savoy Place, London, UK),
ISSN: 0013-5194.
Abstract- The output conductance of gallium arsenide MESFET's, traditionally considered detrimental to device performance, is exploited to affect cancellation of distortion. This occurs in a common-source amplifier with correct loading and provides useful gain. A technique for characterising the device is presented to allow calculation of optimum load for minimum distortion.
Anthony Edward Parker,
"Device characterisation and circuit
design for high performance microwave applications," in IEEE
EDMO'93, London, UK, 18 Oct. 1993.
Abstract- A MESFET model with accuracy extended over a range of operating conditions is obtained by inclusion of secondary aspects of device operation. The model facilitates large-signal and low-signal analysis of distortion and intermodulation for design of high performance analog circuits. Accuracy is obtained with improved device characterisation to fit behavioural trends of device operation. In many applications this is more important than simply fitting traditional I-V and S-parameter measurements.
Danny R. Webster, Anthony Edward Parker, David G. Haigh, and Jonathan B. Scott,
"Effect of circuit parameters and topology on intermodulation
in MESFET circuits," in IEEE GaAs IC Symposium Technical Digest, San
Jose, CA, 10-13 Oct. 1993, pp. 255-258, The Institute of Electrical and
Electronics Engineers, UKISBN: 0-7803-1393-3.
Abstract- Third order intermodulation intercept is a very important criteria in communication circuits and this paper presents a preliminary investigation of the mechanisms responsible. It is shown that interaction of the intrinsic MESFET 2nd order non-linearity with linear circuit and parasitic components can cause significant distortion. MESFET output conductance is shown to cause an interaction effect. Hence, intercept points quite difference from those predicted by standard device characterisation techniques can be obtained. Circuit topology also plays a key role in determining distortion. Some experimental results are given.
A. Khanifar, V. Anand, and Anthony Edward Parker, [eumc93] "Photoparametric amplifier/converter in lightwave communication systems," in European Microwave Conference, Madrid, Spain, 6-10 Sep. 1993, pp. 314-316
ISBN: 0-946821-23-2.
Abstract- The development of a low noise receiver using the photoparametric effect is discussed in this paper. Photoparametric amplifiers are similar to electrical parametric amplifiers with the distinction that they use a photodiode instead of a varactor to perform photodetection and parametric amplification simultaneously. These amplifiers are also capable of performing frequency conversion required in certain applications. The photoparametric amplifier/converter can be used as part of a conventional wideband optical receiver/converter offering improved noise performance or as a low noise detector/converter in microwave subcarrier multiplexed systems. A simulation technique has been developed to optimise amplifier/converter performance and the practical results are presented along with those obtained by analysis and simulation.
David G. Haigh, C. A. Losada, Anthony Edward Parker, and D. R. Webster, [ecctd93] "Systematic approach for the development and design of analogue communication circuits," in Selected Topics in Circuits and Systems, (H. Dedieu, Ed.), pp. 3-74. Elsevier Science Ltd., Amsterdam, Sep. 1993.
ISBN: 0-444-81664-X,
(Tutorial No. 4, {\it European Conference on Circuit Theory and Design}).
Abstract- empty abstract
V. Anand, David G. Haigh, A. Khanifar, C. A. Losada, J. K. Pollard, Danny R. Webster, and Anthony Edward Parker,
"Use of SPICE in
communications research," in IEE Colloquium on SPICE Surviving Problems
in Circuit Evaluation, London, UK, 30 June 1993, number 154 in IEE 1993
Seminar Digests, pp. 12/1-9, The Institution Electrical Engineers, Savoy
Place, London, UKISSN: 0963-3308.
Abstract- Discusses the use of SPICE in a number of projects. All of the projects fall within the communications area but are nevertheless rather diverse, including development of photoparametric low-noise amplifier/converters for optical receivers, high frequency linear and nonlinear transistor circuits and wideband monolithic microwave integrated circuits (MMICs). The authors try to emphasise points about SPICE which are reinforced in these differing projects. They begin with a general review of different nonlinear simulators and a comparison of different versions of SPICE.
Anthony Edward Parker and Jonathan B. Scott,
"New method for
comprehensive characterisation of MES/MOD/MOS-FET's," in Proceedings of
IEEE International Symposium on Circuits and Systems, Chicago, 3-6 May
1993, vol. 2, pp. 1093-1096, The Institute of Electrical and Electronics
Engineers, Inc., New York, NY, USAISBN: 0-7803-1281-3.
Abstract- A measurement technique for performing detailed characterisation of modern field effect transistors (FETs) is reported. The technique, based on impulse excitation over arbitrary voltage and time contours, allows determination of parameters and time constants associated with second-order effects observed in short-channel FETs and III-V semiconductors. Large-signal bias-independent models that incorporate these additional parameters provide predictions that are consistent with large-signal measurements and conventional s-parameter results.
Anthony Edward Parker and David G. Haigh,
"Compensation of 2nd
harmonic distortion in a 4-FET linearised transconductor circuit," in
Proceedings of IEEE International Symposium on Circuits and Systems,
Chicago, 3-6 May 1993, pp. 1089-1092, The Institute of Electrical and
Electronics Engineers, Inc., New York, NY, USAISBN: 0-7803-1281-3.
Abstract- A method of compensation for the second harmonic distortion of a 4-FET linearized transconductor circuit is proposed and evaluated. The sensitivity of the second harmonic distortion level to the compensation parameters is evaluated. Taking account of integrated circuit process parameters, it is concluded that compensation is possible for wide bandwidths up to a decade in frequency. As a first step in understanding the mechanism causing distortion in the circuit, an expression and set of curves showing the effect of signal mismatch in a FET-pair are presented.
Anthony Edward Parker and David James Skellern,
"Improved MESFET
characterisation for analog circuit design and analysis," in IEEE GaAs IC
Symposium Technical Digest, Miami Beach, Florida, 4-7 Oct. 1992, pp.
225-228, The Institute of Electrical and Electronics Engineers, Inc., New
York, NY, USAISBN: 0-7803-0773-9.
Abstract- The third derivative of MESFET drain current behavior is useful for device characterisation. It provides information necessary to devise a model to predict large-signal dynamic behavior with accuracy over an extended range of operating conditions. Extra parameters are proposed to define behavior in sub-threshold and triode operating regions. A continuously differentiable form that models third-order behavior correctly describes these regions. The result is an accurate large-signal model suitable for design and analysis of distortion and intermodulation in analog circuits.
David G. Haigh, P. M. Radmore, and Anthony Edward Parker,
"Advances in linearised GaAs MESFET circuit design techniques," in
Proceedings of IEEE International Symposium on Circuits and Systems,
San Diego, CA, USA, 10-13 May 1992, pp. 2037-2040, The Institute of
Electrical and Electronics Engineers, Inc., New York, NY, USAISBN: 0-7803-0593-0.
Abstract- This paper is concerned with the synthesis of linearized conductance functions using GaAs MESFETs which have an approximately square-law drain current versus gate-source voltage characteristic. The functions for realization are derived and implemented in three basic circuit configurations: transconductance, self-conductance, and buffer function. The new circuits outperformed previous circuits in terms of chip area, power consumption, and efficiency. The alternative concept of voltage linearization is introduced. It was used to realize lossless buffer circuits. Optimization of FET gate widths to allow a verified realistic FET model was demonstrated.
Anthony Edward Parker, David G. Haigh, and C. Toumazou, [iree91b] "Simulation of Gallium Arsenide building blocks," in 23rd International Electronics Convention and Exhibit of The IREE, (J T Harvey, Ed.), Sydney, Australia, 16-20 Sep. 1991, vol. 1 of Proceedings of IREECON'91, pp. 233-236, The Institution of Radio and Electronics Engineers, Australia
ISBN: 0-909394-26-1.
Abstract- The performance prediction of MESFET building blocks important for future high speed GaAs communications circuits is considered. Model simplifications adopted to ease the design procedure can exaggerate circuit performance and lead to unrealistic expectations. Simulations show that second-order and frequency dependence must be included to verify the design.
Anthony Edward Parker, David James Skellern, R. A. Keaney, D. J. Coggins, and S. J. Mahon, [iree91a] "SPICE convergence and charge storage modelling, an expose," in 23rd International Electronics Convention and Exhibit of The IREE, (J T Harvey, Ed.), Sydney, Australia, 16-20 Sep. 1991, vol. 1 of Proceedings of IREECON'91, pp. 229-232, The Institution of Radio and Electronics Engineers, Australia
ISBN: 0-909394-26-1.
Abstract- Problems of convergence and charge conservation are caused by device model implementations which incorrectly use the numerical solver in SPICE. Essential features that must be present in the device model to avoid non-convergence and charge non-conservation are identified. A simple circuit is presented which cannot be analysed without correcting the device model.
Anthony Edward Parker and David James Skellern,
"GaAs device modelling for
design and applications," in Proceedings of IEEE International Symposium
on Circuits and Systems, Singapore, 11-14 June 1991, vol. 3, pp.
1837-1840, The Institute of Electrical and Electronics Engineers, Inc., New
York, NY, USAISBN: 0-7803-0050-5.
Abstract- Device characteristics included in available MESFET models are reviewed, and model extensions for improved accuracy over a wide range of conditions are proposed. Use of the model is illustrated in the context of a basic analog amplifier and analog sub-circuit. The application of other modeling techniques for mixed-mode (analog and digital) systems is briefly discussed.
Anthony Edward Parker,
Design system for locally
fabricated gallium arsenide digital integrated circuits, PhD thesis, The
University of Sydney, Sydney, Australia, 26 Nov. 1990.
Abstract- In order to enable and encourage system designs in the area of Gallium Arsenide (GaAs) circuits, the Laboratory for Communication Science and Engineering at the University of Sydney and the CSIRO Division of Radiophysics have been collaborating to establish a local GaAs digital integrated design and fabrication capability. The aim of this project is to produce a digital GaAs technology compatible with the emerging analog technology so that it can be used in new applications. This thesis addresses both the development of the design techniques needed to produce custom GaAs logic circuits with the low noise fabrication process being developed at the CSIRO and the setting up of design and testing tools which provide circuit simulations, mask layout and assistance in circuit design. The output of this thesis is the forerunner to the establishment of a GaAs logic circuit design facility tailored to the anticipated local capability. The developments reported in the thesis include: an improvement to the SPICE JFET model and an extension of the JFET model to accurately model MESFET's, the development of an automatic system for designing basic logic gates which produces a template BFL gate for the generation of a logic gate library, and the development of a switched-linear modelling technique which features the ability for automatic extraction of gate-level models. An understanding of the operation of the basic gate results in the development of a new high performance logic family. The design system developed in this thesis is an automated link between the fabrication process and design tools. The equations developed allow the derivation of device model parameters for the various passive and active components from the basic physical and electrical properties of the material and devices. This first-principle approach was adopted so that the system can accommodate changes to materials, fabrication techniques and circuit devices. The design system has the long term benefit that it will allow the design facility to keep pace with technological development.
Anthony Edward Parker and David James Skellern,
"Extraction of accurate
switched linear network models for high performance GaAs MESFET logic gates,"
in IEEE GaAs IC Symposium Technical Digest, New Orleans, 7-10 Oct.
1990, pp. 215-219, The Institute of Electrical and Electronics Engineers,
Inc., New York, NY, USAIEEE90CH2889-4.
Abstract- Switched linear network models of MESFET logic circuits allow the investigation of large circuits with accuracy comparable to that obtained with device-level models in SPICE but with far less computational effort. The models achieve computational efficiency and accuracy through a scheme that switches between a small but sufficient number of networks of grounded linear elements which model all relevant regions of gate operation. The models are complete and self-contained, so their interconnection inherently accounts for gate loading. Their structural basis permits automatic generation from a gate circuit description. A procedure for generating switched linear network models for a MESFET logic buffer stage is described. The simulation of a four-bit serial multiplier demonstrates the performance of the switched linear scheme and its excellent agreement with SPICE circuit simulation.
Anthony E Parker and David J Skellern,
"An Improved FET Model for Computer
Simulators," IEEE Transactions on Computer-Aided Design,
vol. 9, no. 5, pp. 551-553, May 1990.The Institute of Electrical and Electronics Engineers, Inc., New York, NY, USA, (New York, NY, USA),
ISSN: 0278-0070.
Abstract- An alternative simple description of FET drain current provides the flexibility of an extra parameter which can be chosen to approximate the Shockley expression or general power-law. An empirical polynomial expression which uses only integer powers is used to provide computational efficiency. The new expression gives the designer a more accurate FET model which is consistent for both large- and small-signal simulations.
A E Parker, D J Skellern, S J Mahon, M L Parrilla, J W Archer, R A Batchelor, G J Griffiths, and W D King,
"Automatic design of GaAs digital
circuits and devices -- from process and material parameters to layout," in
IEEE GaAs IC Symposium Technical Digest, (Kenneth J Sleger, Ed.),
San Diego, CA, USA, 22-25 Oct. 1989, pp. 285-288, The Institute of Electrical
and Electronics Engineers, Inc., New York, NY, USAIEEE89CH2730-0.
Abstract- Sydney University Electrical Engineering and CSIRO Division of Radiophysics have collaborated over the past three years to develop the design techniques and tools needed to build optimised digital circuits for MBE processes geared to low noise microwave and millimetre wave applications. The design approach commences with input of the fundamental process parameters and design rules. From these, SPICE models suitable for use in the design of both linear and digital circuits are automatically generated. These, in turn, are used to automatically design and layout basic logic gates. Simplified models of the gates are extracted for use with a mixed-mode simulator. This entire task from designer entry of parameters, through generation of accurate and simplified models, to layout, can be completed in less than 90 minutes. This paper gives an overview of the design process, describes each of the key problems that had to be addressed in its automation, and shows results of a fabricated circuit.
A E Parker and D J Skellern,
"Switched RC modelling Technique for
GaAs Digital Circuits," in 22nd International Electronics Convention and
Exhibit of The IREE, (M W Austin, Ed.), Melbourne, Australia, 11-15 Sep.
1989, vol. 1 of Proceedings of IREECON'89, pp. 507-510, The
Institution of Radio and Electronics Engineers, AustraliaISBN: 0-909394-17-2.
Abstract- A simple switched capacitor, resister model allows rapid simulating of large GaAs BFL switching circuits. Such a model can be developed and tested against a SPICE reference model. The main benefit gained from the process of extracting the model is the insight into the exact operation of the individual gate elements.
J R Barnes, M L Parrilla, and A E Parker,
"High Performance GaAs
Operational Amplifier Design," in 22nd International Electronics
Convention and Exhibit of The IREE, (M W Austin, Ed.), Melbourne,
Australia, 11-15 Sep. 1989, vol. 1 of Proceedings of
IREECON'89, pp. 486-489, The Institution of Radio and Electronics
Engineers, AustraliaISBN: 0-909394-17-2.
Abstract- This paper investigates the design of a GaAs Operational Amplifier. Simulation of a design with improved gain and frequency performance over existing GaAs Op-Amps is presented. The circuit is suitable for large scale integrated Analogue/Digital systems and high speed applications are discussed.
D Skellern, T Parker, S Mahon, M Parrilla, J Archer, R Batchelor, G Griffiths, and W King,
"GaAs Digital Circuit and Device Design
for Fabrication Processes Geared to Low-Noise Microwave Applications," in
22nd International Electronics Convention and Exhibit of The IREE,
(M W Austin, Ed.), Melbourne, Australia, 11-15 Sep. 1989, vol. 1 of
Proceedings of IREECON'89, pp. 482-485, The Institution of Radio and
Electronics Engineers, AustraliaISBN: 0-909394-17-2.
Abstract- The development of high speed Gallium Arsenide digital circuits for use in mixed analogue/digital integrated systems is presented. A wide range of design activities and tools needed for the development, including material, device, logic gate and system design, are discussed.
A E Parker and D J Skellern,
"Saturated Buffer FET Logic for Gallium
Arsenide Circuits," Lodged for Patent, 17 May 1989.
Abstract- Saturated Buffer FET Logic (SBFL) is a new logic family developed for use in Gallium Arsenide digital integrated circuits. The use of a Swing Limiter diode in conjunction with a Pull-Up transistor in the switch stage of the SBFL gate gives a speed improvement of up to twenty percent over other logic families of similar complexity and a reduction in power consumption. There is no sacrifice in noise margin, and only a marginal increase in wafer area. By eliminating the trade-off suffered when a buffer is included in other logic families, SBFL has switching speed comparable with unbuffered logic families and offers the design flexibility of other high fan-out logic families.
A Parker,
"Gallium Arsenide Integrated Circuits," in ANZAAS Centenary
Congress Program and Handbook, (B O'ROUKE, Ed.), The University of
Sydney, 16-20 May 1988, Australian and New Zealand Association for the
Advancement of Science, Very Large Scale Integrated Circuits, p. 29,
Friar Press LtdUnpublished abstract, 2 pages.
Abstract- Gallium Arsenide (GaAs) is a key `enabling' technology with superior speed-power product that permits the development of systems that have been impossible or impractical to construct using silicon semiconductors. As a result, GaAs integrated circuits are found increasingly in very high performance systems in communications, computers and instrumentation. High performance digital integrated circuits will be especially important for switching and signal processing in future telecommunications systems such as the integrated broadband communications services planned for introduction in the next decade. These will require high speed trunks together with local area and subscriber networks capable of carrying video information to each subscriber. Digital GaAs integrated circuits will be of primary importance in carrying out necessary functions in the links. In order to encourage system designs in these areas in Australia, the Laboratory for Communication Science and Engineering at the University of Sydney and the CSIRO Division of Radiophysics are collaborating to establish a local GaAs digital integrated design and fabrication capability.
A E Parker and D J Skellern,
"Development of GaAs Device Models for
Digital Circuits," in 21st International Electronics Convention and
Exhibit of The IREE, (D J Hutchinson, Ed.), Sydney, Australia, 14-18
Sep. 1987, vol. 1 of IREECON'87 Digest of Papers, pp. 115-118,
The Institution of Radio and Electronics Engineers, Australia.
Abstract- Sydney University's School of Electrical Engineering, in collaboration with the CSIRO Division of Radiophysics, is developing a GaAs digital integrated circuit technology. Simulation for this programme has been approached from a fundamental level so as to develop Schottky diode and MESFET models for the existing SPICE programme. The derivation of model parameters for this purpose has required the detailling of basic GaAs electrical properties. This paper describes these models and how the parameters were derived.
D J Skellern, A E Parker, S J Mahon, J W Archer, G Griffiths, and C J Smith,
"Design and Performance of Locally Fabricated GaAs Digital
ICs," in Microelectronics Conference VLSI 1987 preprint of papers,
(W Carroll, Ed.), Melbourne, Australia, 8-10 Apr. 1987, pp. 144-147, The
Institution of Engineers, AustraliaISBN: 0-85825-346-1.
Abstract- The University of Sydney, School of Electrical Engineering and the CSIRO Division of Radiophysics are collaborating to design and fabricate high-speed Gallium Arsenide digital integrated circuits. The first circuits are based on a depletion mode MESFET technology and will use high quality material grown by molecular beam epitaxy. Transistor gate widths are initially 2 micrometres with 1 micrometre spacing to allow use of local mask-making facilities. This paper outlines the technology being used, discusses circuit design techniques and constraints imposed by that technology, and gives performance estimates for fabricated circuits. The work is targeted primarily at communications applications.